1. Field of the Invention
The present invention relates to a liquid crystal display. In particular, this invention prevents the signal line of a liquid crystal display from opening during fabrication due to stresses caused by thermal expansion or etching.
2. Discussion of Related Art
Generally, a thin film transistor (TFT) performs as a switching device for switching a video signal to an associated pixel of an active matrix (AM)liquid crystal display (LCD). A TFT-LCD includes a plurality of TFTs and pixel electrodes arranged on a bottom glass plate. Additionally, a top glass plate contains a common electrode and color filter, which displays colors. Liquid crystal fills the gap between the bottom and top glass plates. Furthermore, polarizing plates, attached to the surfaces of the bottom and top glass plates, polarize visible light rays.
However, during fabrication of the above-described TFT-LCD, a metal line serving as a signal line may open due to stresses generated between the metal layer and the glass substrate. These stresses are due to differences in thermal expansion (i.e., different coefficients of thermal expansion). It is also possible for the metal layer to become over etched, as described below. Accordingly, yield is frequently reduced.
The coefficient of thermal expansion of the metal layer is different than that of the glass substrate. Therefore, during heating and cooling, the metal layer expands at a different rate than the glass substrate, thereby causing warpage of the glass substrate or breakage of metal lines.
The metal lines may also open during etching. Specifically, the etching process uses an etchant on areas where the metal lines intersect. This intersection area allows the etchant to penetrate the edge of a relatively high portion, that is, the intersection portion, of the metal lines. This penetration results in over etching of the metal line and, possibly an opening or a break in the metal line.
FIG. 1 illustrates a plan view of a conventional liquid crystal display that attempts to solve some of the above problems by incorporating a redundancy line. As shown in FIG. 1, a gate line 1 is formed on a substrate and is coupled to a gate electrode 1A, which forms a TFT region of the liquid crystal display. A data line 3 is formed on the substrate perpendicular to gate line 1. A drain electrode 4 is formed over a portion of gate electrode 1A. Drain electrode 4 is connected to a pixel electrode 5.
Furthermore, a redundancy line 2 of a semiconductor layer is formed along data line 3 and the TFT region, where gate electrode 1A and drain electrode 4 are formed. Here, redundancy line 2 is formed wider than data line 3 where gate line 1 and data line 3 intersect, but it is formed narrower than the data line in region A. Redundancy line 2 is also wider at the TFT region where drain electrode 4 overlaps gate electrode 1A. This prevents the etchant from penetrating the intersection of the metal lines during the etching process.
The conventional liquid crystal display described above, however, suffers from the following problems. Portions over data line 3 extending between the gate line 1 are formed wider than the underlying redundancy line 2, as shown in FIG. 4, which is a cross-sectional view taken along line 4--4 in FIG. 1. As a result, data line 3 frequently has poor step coverage over redundancy line 2, and data line 3 is thinned over edge portions of redundancy line 2. These thinned regions are susceptible to over etching and can cause breaks in data line 3.
Portions of data line 3 that cross over the gate line have widths which are less than the redundancy line 2, as shown in FIG. 5, which is a cross-sectional view taken along line 5--5 in FIG. 1. As further shown in FIG. 5, an insulative layer 15 is provided between data line 3 and gate line 1. Due to differences in the coefficients of thermal expansion between semiconductor redundancy line 2 and metal data line 3, redundancy line 2 and data line 3 expand and contract at different rates in response to changes of temperature. Thus, breaks can occur in data line 3 for this reason also.